The present invention relates to a method as defined in the preamble of claim 1.
In sub-micron generations of silicon-based microelectronic devices (integrated circuits, ICs), titanium disilicide (TiSi2) is the material used for the first level metallization and interconnect of gate structures and active areas. Due to its low resistivity of 16 xcexcxcexa9 cm (compared to poly-silicon: xc2x1300 xcexcxcexa9 cm), TiSi2 is used to reduce the sheet resistance of poly-silicon gates and the active areas. Also, TiSi2 reduces the contact resistance on these areas. A lower sheet resistance and a lower contact resistance result in a lower delay time in circuit (RC-delay), as a result of which the performance level of a circuit is enhanced. As known in the art, the application of TiSi2 has a further advantage relating to IC manufacturing. TiSi2 is formed in a self-aligned silicidation process (salicide process): a titanium layer deposited on a patterned Si/SiO2 structure can selectively form TiSi2 on the areas where titanium is in contact with silicon.
Titanium disilicide is known to have two crystalline modifications: the low-resistivity C54 structure and high-resistivity C49 structure. During self-aligned formation of TiSi2 in a first annealing step the TiSi2 C49 structure is formed. The C49 structure, however, is a metastable phase and can be transformed into the desirable stable C54 structure by a second annealing step. As known to persons skilled in the art, the size of the area where titanium and silicon are in contact during the self-aligned process strongly influences the transformation from the C49 to the C54 structure, which is illustrated by the effective transformation temperature for the transition of TiSi2 C49 to TiSi2 C54. For smaller contact areas, a higher annealing temperature is required to transform TiSi2 C49 to TiSi2 C54. Obviously, with the continuing increase of circuit density (and the accompanying size reduction of on-chip components) from one IC generation to the next, the thermal exposure during TiSi2 formation increases accordingly, which may adversely affect the overall quality of an IC.
Particularly, in semiconductor devices containing MOSFET structures having so-called pinched active areas with a feature size of 0.25 xcexcm or less, proper silicidation of these active areas as well as the gate areas may become troublesome due to limitations in the process window. An overview of the development of advanced Ti silicide processes and their applicability to deep-sub-micron technologies is described by J. A. Kitl and Q. Z. Hong in xe2x80x9cSelf-aligned Ti and Co silicides for high performance sub-0.18 xcexcm CMOS technologiesxe2x80x9d, Thin Solid Films, 320 (1998) pp. 110-121.
It is observed that the reactive ion etching process, which is applied to define these active areas in MOSFETs, forms an impurity layer on the etched openings of Si. In this reactive ion etching (RIE) process, which uses a plasma containing CF4, CHF3, and Ar, the etching process stops at the silicon surface but contaminates the etched openings of Si with carbon, fluorine and hydrogen impurities.
From Japanese patent application JP-A-7-142447, it is known that on a Si/SiO2-patterned surface the impurity layer at the surface of the Si openings actually consists of two layers: a contamination Si top layer and a damaged Si layer below that Si top layer. These Si layers are best removed by a two-step dry etching process in a plasma of CF4 and O2. In the first step, the contamination layer is removed, while in the second step the damaged layer is removed by an isotropic etch of 10 nm Si. In this etching process, also the resist layer is removed. In this document, this RIE process based on a plasma of CF4 and O2 is used for a cleaning step after the formation of the oxide spacers.
From U.S. Pat. No. 5,681,780, a resist strip process is known that combines the etching of a resist layer and the etching of a damaged Si layer in the openings, which damage is caused by a preceding RIE process to form contact openings in an oxide layer on a Si substrate. U.S. Pat. No. 5,681,780 describes a method wherein such a resist strip process based on a plasma of CF4 and O2 is used as a single step process.
It is an object of the present invention to provide a method enabling proper silicidation on so-called pinched active areas of semiconductor devices.
The present invention relates to a method of manufacturing a semiconductor device on a substrate, the semiconductor device comprising at least one active area in the silicon substrate demarcated by spacers; the at least one active area further being arranged so as to be a contact area contacting an interconnect region comprising titanium disilicide; the method comprising the steps of:
Depositing an oxide layer on the substrate;
Depositing a resist layer on the oxide layer;
Patterning of the resist layer;
Etching an opening in the oxide layer to demarcate the at least one active area, by means of a reactive ion etching process, using the resist layer patterned in the previous step;
Removing the resist layer in a dry strip process by means of a microwave plasma comprising at least oxygen as a gaseous constituent;
Depositing a metal layer comprising titanium, on top of the oxide layer and on the at least one active area;
Forming the interconnect region comprising titanium disilicide by a self-aligned process comprising a first annealing step, a selective wet etching step, and a second annealing step;
characterized in that the microwave plasma of the dry strip process comprises a second gaseous constituent, comprising at least fluoride, for cleaning and etching the surface of the at least one active area and isotropically etching the spacers.
Thus, in contrast to the resist strip processes in accordance with the prior art, the etching process according to the present invention using the CF4/O2 plasma of the dry strip process is performed on active areas as a last step before silicidation of these active areas. By applying this etching step as a last step before deposition of Ti (and subsequent silicidation), the sheet resistance of the TiSi2 layer on these active areas is substantially reduced.
Moreover, the present invention relates to a method as described above, characterized in that the second gaseous constituent is carbon-tetra-fluoride CF4.
Furthermore, the present invention relates to a method as described above, characterized in that the width of the at least one active area is 0.35 xcexcm or less, preferably xe2x89xa60.25 xcexcm.
Also, the present invention relates to a method as described above, characterized in that the spacers comprise silicon nitride side spacers.
Thus, the present invention relates to a method which provides an improved phase transformation from the TiSi2 C49 phase to the TiSi2 C54 phase on small-sized active areas and gate areas without the increase in annealing temperature as observed in the prior art. Thus, the thermal budget during manufacturing an IC (i.e. the exposure to elevated temperatures and the respective exposure time) can be reduced and, as a result, the overall quality of the IC may be less affected.